1. Field of the Invention
The present invention relates to a semiconductor device and a driving method of a semiconductor device.
2. Background Art
Such a semiconductor memory device as a NAND type flash memory or the like requires a voltage which is higher than a power source voltage and is constant in order to write, erase or read data. For this reason, a semiconductor device is provided with a booster circuit which boosts a power source and a regulator circuit which holds an output voltage of the booster circuit in a constant voltage.
FIG. 18 shows one example of a boosted potential generating portion in a conventional semiconductor memory device 10. A clock generating circuit 11 outputs a clock signal Φ, and a booster circuit 12 boosts a power source voltage by the clock signal Φ and a reversed signal (hereinafter, called “Φb”) of the clock signal Φ having phases reversed to each other.
A regulator circuit 13 is provided with resistors R1, R2, a differential amplifier AMP1, an inverter In1, and AND gates G1, G2. In a potential detecting circuit 14, the resistors R1 and R2 potential-divides an output potential Vout of the booster circuit 12 to produce a monitor potential MON, and the differential amplifier AMP1 compares the monitor potential MON with a reference potential Vref. The differential amplifier AMP1 outputs “H (High)” level, when the monitor potential MON is larger than the reference potential Vref, while it outputs “L (Low)” level, when the monitor potential MON is smaller than the reference potential Vref. An output signal from the differential amplifier AMP1 is inverted by the inverter In1, and it is inputted into one of input terminals of the AND gates G1 and G2 as a flag signal FLG. Further, the other input terminals of the AND gates G1 and G2 are respectively inputted with clock signals Φ and Φb.
When the output potential Vout is relatively low and the monitor potential MON is smaller than the reference potential Vref, the flag signal FLG is H level. Therefore, the AND gates G1 and G2 allow the clock signals Φ and Φb to pass through the booster circuit 12, so that the booster circuit 12 boosts the power source voltage. On the other hand, when the output potential Vout is relatively high and the monitor potential MON exceeds the reference potential Vref, the flag signal FLG becomes L level. Accordingly, the AND gates G1 and G2 interrupt the clock signals Φ and Φb, so that the booster circuit 12 stop its boosting operation.
Thus, the regulator circuit 13 holds the monitor potential MON in almost the reference potential Vref by allowing passing-through of the clock signals Φ and Φb or by interrupting them. Since the monitor potential MON depends on the output potential Vout, the regular circuit 13 holds the output potential Vout in about a certain constant potential. Thereby, by setting the values of the reference potential Vref and the resistors R1 and R2 properly, the regulator circuit 13 can hold the output potential in almost a predetermined expected potential value.
The above technique is described in JP-A2003-242790 (hereinafter, called Patent Literature 1), U.S. Pat. No. 6,294,950 (hereinafter, called Patent Literature 2) and JP-A08-190789 (hereinafter, called Patent Literature 3).
Now, in order to boost the output potential Vout up to a predetermined expected potential value in a short time, it is necessary to elevate a boosting ability of the booster circuit 12. When the boosting ability of the booster circuit 12 is elevated, as shown in FIG. 19, there occurs such a problem that overshoot and ripple become large. The overshoot means such a phenomenon that a potential transiently exceeds a expected potential value at a time of boosting. The ripple means such a phenomenon that, when an output potential Vout after being boosted is held in an expected potential value, the output potential Vout oscillates at an expected potential value. These phenomena occur due to RC delay from detection of the output Vout to feedback of a flag signal FLG to AND gates G1 and G2.
These problems become significant when the values of the resistors R1 and R2 are made large in order to reduce a value of a current flowing in the resistors R1 and R2, which acts a load current on the booster circuit 12. This is because, when the values of the resistors R1 and R2 are made large, the RC time constant in the potential detecting circuit 14 becomes large so that response of the potential detecting circuit 14 is delayed.
In the Patent Literature 1 and the Patent Literature 2, a semiconductor device which compares a voltage obtained by voltage-dividing an output voltage of a booster circuit with a reference voltage to change a frequency of a clock generating circuit. However, in such a flash memory as an NAND type flash memory, clock signals are ordinarily supplied to a plurality of booster circuits by one clock generating circuit. Thereby, there arises a problem that, when the frequency of the clock generating circuit itself is changed, the frequencies of all the clock signals supplied to the plurality of booster circuits change. On the other hand, when clock generating circuits are provided so as to correspond to each of the plurality of booster circuits, there occur such a problem that the size of the semiconductor memory device is made large and such a problem that the amplitude or the frequency of the clock signal is fluctuated.